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[南京]台积电

职位:2022校园招聘
发布时间:2022-03-23
工作地点:南京
信息来源:贵州大学
职位类型:全职
专业标签:机械类 电气类 自动化 电子信息 工业工程
职位描述
台积电南京2022届招聘简章
2022年3月23日

台积电2022届招聘简章

工作地点:南京

台积电介绍

台积公司成立于1987年,全球专业集成电路制造领域龙头,全球利润率排名第一。拥有281种制程技术,为510个客户生产1万1617种不同产品,拥有52%市场占有率。世界首家提供现今最先进的5奈米制程技术,全世界最大的专业集成电路制造服务公司。

台积电(南京)

台积电(南京)有限公司成立于2016年,位于南京浦口经济开发区,是台积电独资设立的子公司,生产12英寸晶圆,同时成立南京设计服务中心,以最先进的芯片设计技术服务客户。

台积电南京创造了台积很多新的里程碑,包含建厂速度最快、量产最快、获利最快。

校园招聘流程安排:

招募流程:网申→笔试→ (线上+线下)面试→录用通知→加入台积

网申时间:2022/2/17~4/30



职位列表 (所有岗位应届/往届生均可投递)



晶彩台积:对台积人而言,生活的丰富和专业的成就同等重要;从食衣住行的满足到精神层面的提升,台积人在台积获得充分的照顾。

这里拥有:

完善的保险制度:我们除依法为员工缴纳五险一金外,更为员工规划了团体商业保险福利,以增加员工整体之保障。

弹性的假期制度:台积电提供优于劳动法的特别休假制度,员工到职满三个月即可享有,加上弹性的休假制度,方便员工于一年中排定假期。我们并依法给予各种假别,当同仁有请假需求时,能够更无后顾之忧。

贴心的工作环境:我们体贴并照顾同仁的工作及生活所需,在医.食.住.行.乐领域提供全方位的服务与设施,使同仁能轻松兼顾工作与生活。

这里更有:

完善的餐饮及健身设施,贴心关怀的驻厂门诊及全天候的护理协助,免费年度健康检查服务,温馨舒适设施完善的宿舍,多条线路的交通班车贯通供员工免费搭乘,环保典范的工作环境是台积人享有的安心福利。

欢迎志同道合的您加入台积电,一同释放全世界的创新!

申请职位

1.设备工程师(50人)

【职责范围】

1.负责薄膜、黄光、蚀刻、离子扩散、机械研磨等设备机台的维护及效能精进。

2.处理高科技设备故障。

3.提高设备效率。

4.计划和执行分析或缺陷检测项目。

5.与跨职能工程师或供应商沟通。

【职位要求】

1.本科/硕士学历。电子、电气、机械及自动化相关专业。

2.无需经验(有设备维护或改进经验者优先)。

3.具备基本的机械相关知识。有半导体工艺知识者优先。

4.良好的解决问题能力,沟通能力,团队精神,积极的学习态度,英语能力强。

2.制程工程师(10人)

【职责范围】

1.在线问题处理:解决在线制程问题,确保流程的顺畅,协助新制程导入与技术转移,解决工艺异常及减少工艺缺陷,产品良率。

2.计划并执行改进制程良率与降低.制造成本的项目,提升及改善工艺能力。

3.与器件,整合,良率提升,制程整合,制造部等多部门跨部门合作。

【职位要求】

1.良好的解决问题能力,沟通能力,团队精神,积极的学习态度,英语能力强。

2.具有良好的开放式沟通能力,能够在跨职能团队中工作,包括内部和外部合作伙伴。

3.英语流利。

4.较强的统计过程控制(SPC)和/或实验设计(DOE)原理知识。

5.需要基于基础而非经验模型的强大的技术问题解决和分析能力。

6.动手参与和强烈的主人翁精神。

7.可以适应Fab内的工作环境,接受小夜班。

3.制程整合工程师(10人)

【职责范围】

1.确保芯片的质量.持续提升良率,提供给客户具有竞争力且高质量的芯片,让电子产品不但先进且效能稳定;

2.制程整合工程师为半导体制造中的重要协调者,需要与客户沟通了解客制化的芯片应用需求,再将讯息带回厂内,与各工程单位合作,提升产品的良率与质量;

3.良率精进工程师监控芯片的良率与缺陷,使用量测机台监测芯片的缺陷,找出可能的问题,再与制程解决问题。

【职位要求】

1.微电子等相关领域知识的硕士优秀应征者;

2.有较好的半导体组件物理与电性知识/英文与沟通能力/领导与问题解决能力;

3.可将程序语言作为良率改善工具。

4.IC设计工程师 (具体设计岗位如下)(10人)

4.1 SRAM design engineer(静态随机存储器设计工程师)

【职责范围】

1.Develop SRAM/ROM compilers and customized macros.

2.Develop SRAM/ROM characterization flow and deliver design kits.

3.Develop Memory compiler tiling code.

【职位要求】

1.Candidate must have a MS degree or above in Electrical or Computer Engineering.

2.Knowledge on transistor level circuit design and layout design.

3.Experience in spice simulation or fast spice simulation.

4.Familiarity with Verilog and Synopsys .lib.

5.Ability in scripting language, such as Perl/Python/shell/tcl

4.2 Digital circuit design engineer(数字电路设计工程师)

【职责范围】

1.Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)

2.Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)

【职位要求】

1.Good knowledge of circuits design. Experience in digital circuit or ana.log design is preferred.

2.Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred

3.CAD and script capability such as Python/Perl/Shell is preferred.

4.Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.

5.Experience in reliability (EM, high-temperature aging effects, etc.) is a plus

6.Self-motivated and hard work.

4.3 IC Frontend design engineer(芯片前端设计工程师)

【职责范围】

1.RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.

2.Design flow/methodology development and innovation for front-end design challenges.

3.Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.

【职位要求】

1.MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.

2.New graduate or 3+ years working experience.

3.Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.

4.Familiar with tcl/Perl/Python program.

4.4 IC Physical design engineer(芯片物理设计工程师)

【职责范围】

1.Physical implementation of advanced technology chips.

2.Design methodology development and innovation for advanced technology challenges.

3.Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.

4.Be responsible for advanced node PPA benchmark, and solution development.

5.EDA tool new features enablement.

6.Customer onsite/offsite supports will be required on demand.

【职位要求】

1.MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.

2.New graduate or 3+ years working experience in chip physical implementation.

3.Familiar with Synopsys/Cadence APR tools/flows.

4.Familiar with TCL/Perl/Python programming.

5.Experience with TS.MC advanced technology is plus.

6.Proven record in production tape-outs is plus.

4.5 IC CAD and Methodology engineer(芯片计算机辅助设计暨设计方法.论工程师)

【职责范围】

1.Develop chip implementation infrastructure, include but not limited to general design flow automation, design collateral/environment/data management, computing resource allocation/ana.lysis/monitoring, and design diagnosis solutions development.

2.Develop chip implementation methodology algorithms to improve productivity and design PPA by machine learning and/or expert system programming.

3.Develop chip implementation environment regression automation and code review system to improve source code quality and readability.

【职位要求】

1.MS degree or above in EE, CS related fields.

2.Proactive, self-motivated, and willing to take challenges

3.Familiar with Python3 or C/C++ programming languages

4.Familiar with Linux environment and operations

Recommended requirements (plus):

1.Familiar with software engineering or electronic design automation algorithms

2.Familiar with Perl, Tcl/Tk programming languages

3.Familiar with SQL, PHP, Javascript, Html/CCS webpage development

4.Experienced in VLSI design flow and APR tool usage

5.Familiar with data visualization, data mining or machine learning algorithms

6.Paper publication records

4.6 IC Signoff engineer(芯片签核工程师)

【职责范围】

1.Responsible for checking the advanced chip function before fabrication. Given the verification, the chip can exhibit expecting high performance after fabrication.

2.Reliable flow setting, identify violation root cause, and provide the fixing strategy to achieve high quality chips.

3.Professional at one domain of blow knowledge at least. Signoff team not only executes the advanced signoff skill, but also push the boundary of flow to reach higher quality and productivity.

a.STA (static timing ana.lysis): using commercial timing signoff EDA tool combining advanced on-chip timing ana.lysis method (OCV) to achieve timing closure before tape-out.

b.IR ana.lysis: define the reasonable IR drop spec, and explore the opportunity to realize the function with sufficient voltage support and reasonable power consumption.

c.PV (physical verification): verify and achieve the chip without DRC (design rule check) and LVS (layout versus schematic). With the verification, the following fabrication can minimize the defect and reach high yield performance.

【职位要求】

1.MS degree or above in EE, CS, Physics or related domains. Experience in Digital IC design flow, especially signoff, is a plus

2.Innovative, persistence and flexible personality.

3.For frequent cross team cooperation and customer support, excellent communication/presentation skill

Recommended requirements (plus):

1.Excellent English skill, CET6

2.Software skill, ex: tcl, python

4.7 Layout Engineer(IP版图设计工程师)

【职责范围】

1.Full layout design for standard cell/IO/SRAM IPs in advanced process nodes

2.Work on the physical verification (DRC/LVS/Antenna ...)

3.Work on test chip layout design and verification

4.Close cooperation with designers on PPA optimization

【职位要求】

1.At least BS Degree of Microelectronics or Physics.

2.Excellent graduate or at least 1 years' related working experience

3.Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)

4.Familiar with design rule and layout effect in advanced process.

5.Excellent skills of communication and teamwork are also expected.

6.Programming experience (Perl/tcl skill) will be a plus.

7.Experience in advanced process (n16 and beyond) will be a plus.

4.8 DRC/LVS Development Engineer(DRC/LVS开发工程师)

【职责范围】

1.Work closely with process RD team to develop DRC/LVS for design readiness.

2.Provide customer support to world-wide leading design house.

3.Initial more innovation to continue optimize development efficiency.

4.Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.

5.Work closely with EDA partner for tool qualification and methodology enhance.

【职位要求】

1.Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.

2.Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.

3.Scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.

4.Ability to work across teams to drive a solution, problem solver and self-motivated.

5.The ideal candidate will have experience in DRC/LVS development.

6.MS or above in EE, CS related fields.

5.智能制造工程师(5人)

【职责范围】

1.创造晶圆产出最大化,满足客户交期,为公司带来营收。

2.掌握生产流程,藉由良好且精准派工提升机台生产效率,带领技术员团队确保制造流程顺畅运行并达成每日的产能目标。

【职位要求】

1.工业工程、制造工程、资讯工程、商管统计知识

2.运用大数据分析、机器学习优化生产排程

3.领导力与沟通技巧,抗压能力需具备OM,IE或IT相关领域。

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