Responsibility：
1. Design the circuits of IPs used in memory products, including DLL, CMD controller, data path, DFT etc.
2. Simulate, verify and analyze memory functionality and performance.
3. Optimize the circuit timing margin under different PVT conditions.
4. Make documents for the block descriptions.
5. Cooperate with PT for post silicon results debugging.

Requirement:
1. Good knowledge and deep understanding CMOS circuit design.
2. Familiar with EDA design tools such as spectre, hspice, finesim, Virtuoso etc.
3. Experience in memory design is preferred.
4. Good team player and communication skills.
5. Good learning competency, self-motivated in a flexible and dynamic environment.