关键要求：电子工程硕士，1年以上模拟电路设计，擅长PLL，CDR，TIA，Laser Driver，Equalizer，SerDes等任一方向

Job Responsibilities:

1. Design, analyze, and implement high-performance (＞10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, ToF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
2. The design of high-frequency (multi-gigahertz) and high-precision clocking and analog circuits.
3. Use EDA tools (Cadence, Mentor) to run simulation and function verification.
4. Guide layout engineer to optimize layout.
5. Chip debug and testing individually and with the team.
6. Other tasks assigned by line manager.

Qualifications:

1. MSEE in analog IC design with no less than 1 years experience. Exceptional fresh Master or PHD is considered.
2. Experience in Cadence EDA tools.
3. Team player with good communication skills.
4. Experience with multi-gigahertz SERDES transmitter/receiver, TIA, PLL, CDR, LNA etc. is highly preferred.
5. Desired: Knowledge of advanced circuits such as PLLs, ADCs, DACs, LNAs, drivers, NF, S-parameters, BW extension, impedance matching.
6. Desired: Experience in RF circuit design, testing, and post-silicon bring-up and evaluation.