Responsibility
1. Design the circuits of IPs used in memory products
2. Gate-level circuit design of digital blocks, and mix-signal simulation
3. Simulate, verify and analyze memory functionality and performance.
4. Optimize the circuit timing margin under different conditions.
5. Make documents for the block descriptions.
6. Cooperate with PE/TE for post silicon results debugging.
Requirement:
1. Good knowledge and deep understanding CMOS circuit design.
2. Verilog or RTL level design is plus.
3. Familiar with EDA design tools such as spectre, hspice, finesim, Virtuoso etc. VCS, NC-verilog, System-Verilog is a plus.
4. Experience in memory design is preferred.
5. Good team player and communication skills.
6. Good learning competency, self-motivated in a flexible and dynamic environment.