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SoC RTL Design and Integration Intern300元/天
更新于07月07日
职位描述
Responsibilities:
1. Participate in DFT feature and architecture definition for complex SoC
2. Implement DFT logic/circuit including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
3. Generate DFT related timing constraints and support timing closure with backend engineer
4. DFT test patterns generation, simulation and debug
Requirements:
1. Bachelor or master degree, majoring in microelectronics, electronic engineering, computer science or related
2. Strong Verilog and C coding skills
3. Good knowledge of digital IC design
4. Familiar with on-chip bus protocols (AXI/AHB or similar) is a plus
5. Good English communication skills
1. Participate in DFT feature and architecture definition for complex SoC
2. Implement DFT logic/circuit including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
3. Generate DFT related timing constraints and support timing closure with backend engineer
4. DFT test patterns generation, simulation and debug
Requirements:
1. Bachelor or master degree, majoring in microelectronics, electronic engineering, computer science or related
2. Strong Verilog and C coding skills
3. Good knowledge of digital IC design
4. Familiar with on-chip bus protocols (AXI/AHB or similar) is a plus
5. Good English communication skills
公司信息
恩智浦（中国）管理有限公司
外资（欧美）·电子技术/半导体/集成电路