Responsibilities:
1. Responsible for leading-edge chip and block level RTL synthesis, logic equivalent check, clock tree synthesis, P&R, STA
2. Responsible for floor-plan, power integrity and physical verifications
3. Tight collaborations with global peer teams from various functions

Requirements:
1. Master degree, major in microelectronics, electronic engineering , computer science or relevant disciplines
2. Knowledge and experience in SoC design, with backend ones being a plus
3. Script coding ability Perl/TCL/Python in Linux/Unix environment
4. Excellent communication skills and collaboration spirit