职位名称：数字前端设计/验证工程师

职位描述：
1. 独立完成ASIC功能模块的设计任务，包括：需求分析，架构定义，模块设计，逻辑综合和时序分析；
2. 独立完成ASIC功能模块的验证任务，包括：制定验证方案，搭建测试环境，编写测试用例等；
3. 负责芯片顶层及子模块的逻辑综合和时序分析；以及相关DFT RTL代码编写，扫描链，MBIST电路，边界扫描电路插入，以及测试pattern的生成及仿真等；
4. 作为芯片的设计者，配合系统工程师、物理实现工程师和测试工程师，解决功能验证、平面布置图设计、时序优化/收敛、可测试设计和芯片测试方面的问题。

职位要求：
1. 硕士及以上学历，电子工程或计算机科学相关专业；
2. 熟悉RTL Coding/UVM（Verilog/SystemVerilog）；
3. 熟悉ASIC的设计流程，特别是从规格文档到架构定义，再到RTL实现、验证和综合；
4. 熟练应用EDA工具（Synopsys或Cadence）：VCS、Xcelium、DC、PT等；
5. 熟悉C/C++语言、Perl、Python等脚本语言；
6. 熟悉SOC片上总线协议如AMBA、NOC的优先；
7. 有ARM、RISC-V、GPU、DSP、VPU、NPU、ISP、Display IP等处理器设计背景优先；
8. 有USB、PCIe、CXL、UCIe、Ethernet、DDR、UFS、DP等接口背景的优先；
9. 有相关AI辅助设计及机器学习在IC设计中应用经验者优先；
10. 富有事业心和团队合作精神，良好的中英文听说读写能力。

工作地点：上海/成都/南京/广州

Title: ASIC Design/Verification Engineer

Responsibilities:
1. Independently work on the design of ASIC functional blocks in terms of requirement analysis, architecture definition, block design, logic synthesis, and timing analysis (STA).
2. Independently work on the verification of ASIC functional blocks in terms of verification plan, test bench building up, test case development, and other related tasks.
3. Perform logic synthesis and timing analysis of chips and sub-blocks, as well as DFT RTL coding, scan chain/MBIST/boundary scan circuits insertion, and test pattern generation and simulation.
4. Work closely with system engineers, physical implementation designers, and testing engineers to complete functional verification, floorplan design, timing optimization/closure, and DFT & ATE testing.

Requirements:
1. Master's or above degree in EE/CS related majors.
2. Familiar with RTL coding/UVM (Verilog/SystemVerilog).
3. Familiar with the ASIC design flow, including specification, architecture definition, RTL coding, verification, and synthesis.
4. Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium, DC, PT.
5. Familiar with C/C++, Perl, Python, or other programming language.
6. A knowledge of SOC on-chip bus protocols (AMBA/NOC) is a plus.
7. A knowledge of processor design (ARM, RISC-V, GPU, DSP, VPU, NPU, ISP, Display IP) is a plus.
8. A knowledge of interfaces such as USB/PCIe/CXL/UCIe/Ethernet/DDR/UFS/DP is a plus.
9. Experience in AI-assisted design and ML applications in IC design is a plus.
10. Self-motivated and a good team player. Good communication skills in both Chinese and English in either listening, speaking, reading or writing.

Location: Shanghai/Chengdu/Nanjing/Guangzhou