职位名称：版图设计工程师 (Layout Design Engineer)

职位描述：
1. 根据电路设计要求，参与开发模拟及混合信号/基础IP等CMOS深亚微米IP设计版图；
2. 完成物理验证及寄生参数的抽取；
3. 根据公司设计流程产生数据包。

职位要求：
1. 本科及以上学历，微电子学或电子工程等相关专业；
2. 熟悉Unix/Linux操作系统，熟悉Synopsys/Cadence/Mentor或相关EDA软件的使用，熟悉Shell/Skill/Tcl/Perl等脚本语言者优先；
3. 具有版图设计经验，熟悉IC设计流程以及芯片制造工艺者优先；
4. 具有模拟及数字电路基础者优先；
5. 富有事业心和团队精神，有奉献意识，积极主动，沟通表达能力良好。

Job Description:
1. Participate in developing layout designs for CMOS sub-micron IPs, including analog, mixed-signal, and foundation IPs, based on circuit design requirements.
2. Complete physical verification and parasitic parameter extraction.
3. Generate data packages according to the company’s design flow.

Qualifications:
1. Bachelor’s degree or above in Microelectronics or Electronics Engineering, or related fields.
2. Familiarity with Unix/Linux operating systems and experience in using Synopsys/Cadence/Mentor or related EDA software. Proficiency in scripting languages such as Shell, Skill, Tcl, or Perl is preferred.
3. Prior experience in layout design, familiarity with IC design flow, and knowledge of chip manufacturing processes are preferred.
4. Strong foundation in both analog and digital circuits is preferred.
5. Self-motivated, dedicated, and proactive, with good communication and teamwork skills.

工作地点：广州、合肥
Base: Guangzhou、Hefei