职位名称：数字电路设计/验证工程师 (Digital Design/Verification Engineer)

职位描述：
1. 负责SoC和高速SerDes IP的设计与实现，包括：算法设计，RTL编程，模拟设计建模，验证，综合，时序收敛以及芯片调试；
2. 负责SoC和高速SerDes IP的验证，包括：搭建UVM验证平台，制定验证计划，开发测试pattern；
3. 作为IP设计者，和模拟设计团队协同进行接口的定义，和验证团队合作以便顶层测试环境的整合，和产品团队协作使产品或IP达到量产标准。

职位要求：
1. 硕士及以上学历，计算机科学或电子工程相关专业；
2. 有相关集成电路设计/整合/验证工作（包括课程项目）经验；
3. 有SerDes高速接口电路设计验证和integration经验者优先；
4. 有UVM/System Verilog/C/Perl/Python经验者优先；
5. 有DFT经验和时序分析经验者优先；
6. 富有事业心和团队合作精神，沟通表达能力良好，中英文沟通顺利。

Job Description:
1. Responsible for the design and implementation of SoC and high-speed SerDes IP, including algorithm design, RTL programming, analog design modeling, verification, synthesis, timing closure, and chip debugging.
2. Responsible for the verification of SoC and high-speed SerDes IP, including building UVM verification platforms, developing verification plans, and creating test patterns.
3. As an IP designer, collaborate with the analog design team to define interfaces, work with the verification team to integrate into the top-level test environment, and collaborate with the product team to achieve production standards for chips or IPs.

Qualifications:
1. Master’s degree or above in Computer Science or Electronics Engineering or related fields.
2. Experience in integrated circuit design/integration/verification work (including coursework projects).
3. Preferred experience in SerDes high-speed interface circuit design, verification, and integration.
4. Preferred experience in UVM/System Verilog/C/Perl/Python.
5. Preferred experience in DFT and timing analysis.
6. Self-motivated, with good teamwork and effective communication skills in both English and Chinese.

工作地点：广州、合肥
Base: Guangzhou、Hefei