职位描述
Digital verification engineers are capable of performing functional and system-level verification of digital and mixed-signal chips using advanced verification methodologies and industry-standard ASIC tools. Products include a variety of mixed-signal and SoC chips for power management, automotive electronics, LED lighting, networking, and charging.
Responsibilities:
1. Complete the verification work of digital and mixed-signal chips.
2. Build a verification platform, test cases, and write module -level /system-level verification models.
3. Write verification documentation to record test results and coverage.
4. using Verilog, System Verilog, UVM, test cases, and verification IP.
5. Need to master one or more of the following design tools and processes: RTL simulation, coverage analysis, netlist-level simulation, mixed-signal simulation, etc.
6. Assisting with testing and FPGA verification.
Requirements:
1. microelectronics, electrical engineering or a related field.
2. ASIC SV/UVM verification or related fields is preferred.
3. Good reading, writing and speaking English skills and team communication skills.
4. Able to independently follow process rules and complete tasks to a high standard.
5. Familiar with Perl/TCL/Unix/Python scripts.